Integrating printed electronics and PCB technologies

 

The Printed Circuit Board industry is about to become green through the introduction of printed electronics manufacturing processes being developed.

 

Currently, very few PCB manufacturers are making money, being restricted by the high costs of complex capital equipment, high labor content, soaring energy costs and a multitude of consumables, which for the most part end up in a waste stream or landfill.

 

PEC (printed electronic circuits) will have the ability to eliminate the required traditional subtractive wet process and green the entire process. PEC has the capacity even at this early stage to breach the technology wall.

 

This green technology is a full additive process which automatically eliminates the need for any etching, stripping, metalizing, copper plating. Formaldehyde, chelators, ammonia, heavy metals, acids or electroless processing therefore eliminates the entire wastewater treatment systems.

 

PEC allows the interconnection of the circuitry to be accomplished by highly conductive Nano inks without the need to drill holes. By eliminating the drilled via hole, PEC increases reliability of the interconnect. The vias are 100% filled with silver ink and have equal resistance to a drilled plated via. The special PEC conductive inks allow a drilled hole to be filled with silver and re-drilled smaller to create a very strong conductive through hole if desired.

The PEC process is performed with MINIMAL equipment requirements and is made with 10% of the capital outlay when compared to the subtractive process. Out of the box, PEC will surpass the current incumbent technologies in small line width and spaces producing multilayered high density PCB's without multilayer equipment.

Without the huge costly wet processes and metal finishing, significant savings occur in labor, equipment and water consumption.

 

These savings repeat themselves by way of wastewater treatment and sewer user fees. Electric and gas consumptions see a remarkable reduction by eliminating the need to heat most of the wet processes, multilayer presses, as well as the large plant wide demand for compressed air. HVAC reductions are also experienced due to greatly reduced exhaust requirements.

With the reduced amount of the many complex chemical processes to monitor, high overhead labor is eliminated. PEC is expected to use 20% of the current labor requirement with the same sq. ft. output.

The actual processing steps of PEC were introduced several years ago and were successfully used in special application VHDI designs. Using a method to create a trench into a dielectric, conductive polymer inks were used to fill these trenches. The results were flush surface circuitry with interconnect accomplished by filling holes or the created voids with conductive inks. The missing link in this process was the availability of the proper materials to work with. Mr. Robert Tarzwell, well familiar with the technique began to experiment with new materials born out of the RFID and Solar Cell technologies.

 

The PEC line of proprietary Nano Technology Conductive Silver and Ceramic Dielectric inks makes for an entrenched technology circuit to nearly equal the resistance properties of etched copper, encapsulate all conductors within a ceramic filled Dielectric with high resolution. This entrenching method allows us to control both the thickness and the width of the conductor and therefore the overall resistance of the trace.

Various other methods to print the silver or copper Nano ink were tested - ink jet and screening technologies. Both proved to have problems we could not easily live with manufacturing a typical PCB.

 

The ink jet could not lay down a thick enough trace to be of use and if we layered down 4-6 times to get thicker traces to achieve resistance criteria, the printing speed was too slow and the trace grew wider from positional accuracies and over spray.

 

Similar problems were experienced with trying to screen on traces. Nano inks are expensive and excessive loss was experienced. Bleed also was a problem, which was not easy to overcome due to the nature of the special ink and screen properties.

 

However, the PEC entrenching technique, we can very accurately control both the width and depth. The surface of the board remains flat, which is a desired SMT assembly characteristic.

 

Line widths of 2 mils (50 microns) "out of the box" are very producible with up to 4 mils (100 microns) in dielectric thickness. Our latest Nano ceramic photo imageable ink has shown to resolve down to .7 microns or 1/3 mil allowing microcircuits designs to be realized.

The initial testing to date has been aimed at producing fine lines, through vias and via in pad.

 

To manufacture a through via we first drilled a hole the size of the pad, fill it with basic via fill silver epoxy ink, cure the ink then drill through the middle with the smaller via hole. Our test have shown the resistance of a 3 to 4 mil (75 to 100 micron) silver wall to be the same as a 1 mil (25 micron) copper plated wall.

 

Testing for thermal cycling reliability of the through holes is next on the agenda and we will report as to our findings.

 

With the via in pad proven, we manufactured perfectly flat pads with a connection of a short silver filled solid post to the next layer down, something the typical plating technology cannot do easily. We still have some problems to sort out with the resistance and viscosity of the PEC Nano silver inks but we are assured by engineering that we can get the viscosity just right to squeegee in to the trenches effectively and reach our goal of nearly equaling copper's resistance.

 

The work done to date proves that printed electronics are capable of replacing almost any PCB manufactured today with less equipment and significantly less pollution and labor with the built in capability of even finer technology.

 

Stage 2 will soon be performed with the goal to create fine line, high layer count, buried and blind via multilayer with expected lowered resistance levels.

Stage 3 will be aimed to test PEC for the current PCB required reliability tests, thermal, flex, ionic contamination, flatness, voltage dielectrics, ark over properties and solderability.

 

With the current difficulties that all PCB manufacturers face today, it becomes clear that investigating the PEC process could be that breath of fresh air needed by the industry at large.

 

Guest article written by:

Robert Tarzwell, President of www.dmrpcb.com , email and Mike DuBois, Caledon Controls Ltd. exclusive distributor for PEC silver bullet, email .

 

Robert Tarzell will be presenting at the IDTechEx Printed Electronics USA 2009  conference and trade expo covering "The PCB Industry - Is it ready for the printed electronics onslaught?"