Researchers from the Nanoelectronics Research Institute (NeRI) and the National Institute of Advanced Industrial Science and Technology (AIST) have developed a graphene transistor with a new operating principle, in collaboration with Innovation Center for Advanced Nanodevices (ICAN) and the National Institute for Materials Science (NIMS).
In the developed transistor, two electrodes and two top gates are placed on graphene and graphene between the top gates is irradiated with a helium ion beam to introduce crystalline defects. Gate biases are applied to the two top gates independently, allowing carrier densities in the top-gated graphene regions to be effectively controlled. An electric current on/off ratio of approximately four orders of magnitude was demonstrated at 200 K (approximately −73 °C). In addition, its transistor polarity can be electrically controlled and inverted, which to date has not been possible for transistors. This technology can be used in the conventional production technology of integrated circuits based on silicon, and is expected to contribute to the realization of ultra-low-power-consumption electronics by reducing operation voltage in future.
In recent years, the increase in power consumption associated with the spread of mobile information terminals and the progress in IT devices has become a concern. Societal demand for reduction of the power consumed by electronic information devices is increasing. Although attempts at reducing the power consumed by large-scale integrated circuits (LSIs) have been advanced, the conventional transistor structure is considered to have inherent limits. Meanwhile, electron mobility of graphene, which represents the ease of electron movement, is at least 100 times larger than that of silicon. It is also expected that graphene can be used to resolve the problems of the inherent limits of silicon and other materials.
Therefore, graphene has the potential to remove the obstacle to reducing the power consumed by LSIs, and it is expected that graphene will be used as a material for ultra-low-power-consumption transistors of the post-silicon age that utilize new functional atomic films.
However, when graphene is used in a switching transistor, electric current cannot be sufficiently interrupted, because graphene has no band gap. Also, although there is technology for forming band gaps, electron mobility decreases when the band gap required for switching is formed. Therefore, a graphene transistor with a new operating principle that can perform the switching operation effectively with a small band gap is required.
In order to demonstrate the transistor operation of the new operation principle, a transistor was fabricated by forming source and drain electrodes and a pair of top gates on a single-layer graphene isolated from graphite. An appropriate dose of helium ions was applied between the top gates to make a helium ion irradiated channel and the outer unnecessary graphene was irradiated with a heavy dose of helium ions to make it an insulator. As a result, the transistor channel is 20 nm in length and 30 nm in width.
On/off operation of the fabricated transistor was performed at the low temperature of 200 K (approximately −73 °C). The source and drain terminals were applied with biases of −100 mV and +100 mV, respectively. The gate bias of the drain-side gate was fixed at −2 V, and that of the source-side gate was swept from −4 V to +4 V and the electric current flowing between the source and drain electrodes was measured. An on/off ratio of approximately four orders of magnitude was observed.
In the developed transistor, the on state or off state is controlled according to whether the polarities of the voltages applied to the two top gates are the same or different. Therefore, by fixing one gate bias and changing its polarity, it is possible to control whether the transistor operation by sweeping the other gate voltage is n-type or p-type. In the present experiment, voltages of −100 mV and +100 mV were applied to the source and drain terminals, respectively.
The researchers are aiming to realize CMOS operation in which transistor polarities can be changed through electrical control. They are also aiming to create a device prototype using a large-scale wafer with graphene synthesized by the CVD method (chemical vapor-phase deposition method). At the same time, efforts to achieve higher-quality graphene will be made in order to improve the on/off ratio of electric current at room temperature and carrier mobility.
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Learn more at the next leading event on the topic: Graphene USA 2019 on 20 - 21 Nov 2019 at Santa Clara Convention Center, CA, USA hosted by IDTechEx.