Reliability and performance issues are technical challenges in packaging solutions for compact sized consumer electronics and high power electronics. To address these issues, the A*STAR Institute of Microelectronics (IME) and leading semiconductor companies have joined to form the 12th Electronics Packaging Research Consortium (EPRC12). By leveraging on the experience and knowledge of the members, the consortium aims to address the package design, materials and process integration challenges for improved packaging solutions.
EPRC12 consists of 11 members spanning the semiconductor supply chain of the industry from integrated device manufacturers, foundries, packaging houses, to equipment and material companies. Members include Ajinomoto, EV Group, GLOBALFOUNDRIES, Heraeus Materials, Henkel, Infineon Technologies, JSR Micro N.V., Linxens, Tokyo Ohka Kogyo, Academy of Public Security Technology (Hefei) and one other packaging company.
The consortium will focus on three projects to develop advanced technologies for (a) Copper (Cu) pillar interconnect, (b) embedded wafer level packaging (EMWLP) for 3D integrated devices and (c) high power electronics packaging solutions. The Cu pillar project will address the thermo-mechanical issue of the interconnect structure to provide an improved structural integrity for fine pitch interconnection in applications such as processors for consumer electronics. The 3D-EMWLP project will develop solutions to improve the electrical performance for Package-on-Package (PoP) application with medium to high through-mold interconnections.
The power electronics packaging project aims to develop a novel packaging solution for power module with junction temperature up to 220°C for wide bandgap applications in aerospace, green and renewable energy, as well as future automotives such as hybrid electric vehicles or electric vehicles.
"Supply chain alliances with intersections amongst tool suppliers, foundry, packaging companies, and the system designers, aided by consortia has proved to be a good working model in the fast-changing, highly complex world of advanced packaging," said Prof. Dim-Lee Kwong, Executive Director of A*STAR IME. "With the launching of 12th EPRC, it is heartening to observe that the EPRC consortium, first launched in 1996, continues to serve as a strategic platform for our industry partners to leverage our extensive experience and cutting edge capabilities to develop timely solutions. Through the consortia, better chip performance and reliability, smaller form factor and increased functionalities have been achieved."
"EVG's extensive experience and integrated capability for thin wafer handling and processing of warped wafers on the state of the art "Gemini" platform will significantly contribute to ensure successful backside ViM processing utilizing TBDB technology," said Frank Huysmans, Asia Pacific sales manager, EVG.
"Participating in the consortium is a real must for Linxens not only for the value it brings to all members but also as a member of the industrial community of Singapore. We are proud to contribute our knowledge and expertise to the future of IC design," said Olivier Castaignede, strategy director in Linxens.
Source: A*STAR Institute of Microelectronics
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