Last week IDTechEx attended and presented at an event on thin film transistors in Portugal. This event brought together researchers from across the globe.
Participants included Imperial College London, University of Cambridge, Tokyo Institute of Technology, Yonsei University, University of Tokyo, Universidade Nova de Lisboa, Korea Advanced Institute of Science and Technology, LG Display R&D Centre, Evonik, Waseda University, Sungkyunkwan, Ecole Polytechnique, Delft University of Technology, VTT, Max Planck Institute of Solid State Research, Nara Institute of Science and Technology, etc.
Here is our summary of the latest work in this rapidly expanding field.
Oxide semiconductors are considered the leading candidate for the next-generation of TFT technologies. This is because they offer the following excellent attributes: (a) high mobility values (>10 cm2/Vs), (b) high transparency (bandgap >3 V), (c) low temperature processibility, (d) high spatial uniformity (the material is amorphous) and (e) high temporal stability (the bonding is ionic).
These attributes make them the best candidate for driving large-area OLED displays. This is because the well-established amorphous silicon struggles with supplying the drive currents demanded by OLEDs, while polycrystalline silicon struggles with achieving the required spatial uniformity over large areas due to grain boundary effects.
This class of materials is often based on ZnO. In a typical implementation, indium is introduced to increase the carrier mobility while gallium (or hafnium, zirconium, silicon, etc) is to control the carrier concentration (and thus the threshold voltage).
These devices are typically sputtered. However, in the past few years we have witnessed a rapid growth in the reports on the solution processing of oxide semiconductors. The main challenge here lies in lowering the annealing temperature, which has typically been as high as 600⁰C.
In this regard, the latest reports demonstrate that GaInZnO TFTs can be synthesised using a sol-gel process with an annealing temperature as low as 230⁰C. This could pave the way for printing oxide TFTs on low-cost flexible substrates.
Recent reports also demonstrate the photo annealing of solution-processed GaInZnO TFT in ambient and at room temperature. Here, a UV light is used with an intensity of only 30mW/cm2 for several tens of minutes. The resultant TFTs have excellent current-voltage characteristics.
This could also pave the way for printing oxide TFTs. In fact, this fits well in the context of printing electronics where photo-annealing is used to cure various nanoparticle based conductors.
Innovation in the manufacture of oxide semiconductors does not stop here. This is because oxide semiconductors can also be deposited using a spray technique, which is an excellent approach for covering large areas. The reported channels are mainly based on polycrystalline ZnO. The annealing temperatures are however still as high as 500⁰C but this could be reduced in the future.
Not all is perfect with oxide semiconductors however. Looking into the future, several issues remain. These include improving the stability of oxide TFTs, particularly under optical illumination. This is the case because a range of different instability mechanisms and sources have been identified.
These include the adsorption/desorption of ambient species, ionisation of oxygen vacancy sites, charge trapping at the channel/dielectric interface.
The question of the best dielectric layer is also still not settled. The challenge here originates from the fact that oxides are wide bandgap semiconductors. This means that the technologically-important SiNx (bandgap= 5.1 eV) does not work well. This is the case because the valence band offset (the difference between the valence levels of the dielectric and the semiconductor) is very small, resulting in instability particularly when the device is subjected to negative-bias-illumination stress (the prevalent condition in active matrix backplanes).
An interesting solution being followed aims at using a double or triple layer dielectric in which an insulating material with high-k and low bandgap is combined with one having a low-k but high bandgap. The absence of p-type conductivity in most oxide semiconductors is also a challenge in that it results in the absence of complementary logic. P-type conductivity is difficult to attain due to a variety of reasons, the most important being that ZnO has so-called /'compensation centres'/, which are defect states that spontaneously form to maintain the material in a state of n-type conductivity.
Today, several oxide semiconductors offering p-type conductivity are being researched. The favoured candidate is Cu2O. The challenge here is that processing windows (sputtering conditions in terms of pressure, time, gases, target, etc) is extremely narrow and so it is still hard to get reproducible results even on the lab scale.
Another TFT technology emerging is based on carbon nanotubes (CNTs). CNT TFTs are shown to be highly flexible. In fact, recent reports demonstrated that no change in CNT transistor performance occurs when the device is bent 180 degree!
CNTs are mainly p-type conductors but they can be doped n-type using a viologen surfactant. This is useful because it enables realising complementary logic. In the reported implementation, the passivation layer was in some parts based on SiOx (resulting in a p-type device) and in other parts based on the surfactant(resulting in n-type device). NOR and NAND logic gates were reported.
Carbon nanotube TFTs suffer from an inherent trade-off between ON/OFF ratio and mobility. The reason is that to increase the mobility, a high density CNT film (more CNTs per unit area) is deposited. This in turn gives rise to more parasitic conduction paths, resulting in a high OFF current.
The main approach towards softening the trade-off is based on purifying the CNT network (removing the 'metallic' ones). In this approach, CNTs are typically covered with surfactants which selectively attach either to metallic or semiconducting CNT. The solution is then put though a centrifuge system, which separates the two. Even this approach does not entirely eliminate the trade-off. Another downside is that surfactants bind strongly to the CNT therefore it is difficult to remove them. This in turns results in a degradation of the field-effect mobility.
Organic semiconductors have been researched for decades. The progress in field-effect mobility has however slowed down. It now looks likely that the mobility levels will plateau below 12cm2/Vs, even for the best vacuum-processed systems deposited under laboratory conditions.
In spite of this, new organic semiconductors are being reported. One example is DPP (diketopyrrolopyrole) based co-polymers. This is an ambipolar system in which both electron and holes contribute to the current conduction. Both electron and holes could have mobility levels as high as 1cm2/Vs. The ambipolar nature was shown to result in light emission over a narrow area where electron and holes recombine to emit light. These devices were also shown to be more stable in air than other several organic systems.
Silicon can now be printed directly from the liquid phase. The resultant TFTs are polycrystalline, giving mobility values in the range of 391 cm2/Vs (electron) and 111 cm2/Vs (holes).
The main advantage is that printing is additive, resulting in high material utilisation. The main challenge is that the annealing temperature is in excess of 400⁰C which is too high for realising printed TFTs on low cost cheap substrates. This could change in the near future.
Ionic gels are being considered as dielectrics. Here the dielectric capacitance is very high due to the double-layer effect (i.e., a very narrow charge sheet is formed at the interface between the gel and the semiconductor). This gives rise to high mobility, particularly when applied to CNT or graphene based devices.
The main issue here is that these devices are inherently slow (the ions take time to move) and there is a huge hysteresis in the system. We do not consider this technology as being technologically significant in the near to medium term.
For more information on TFTs please refer to: Printed and Thin Film Transistors and Memory 2011-2021.
For more information Printed Electronics Europe 2012 in Berlin, Germany on April 3-4 features sessions dedicated to covering the latest work on thin film transistors and memory.